Synthesis Report #Build: Synplify Pro (R) W-2024.09LR-SP1-1, Build 155R, Jun 12 2025 #install: C:\lscc\radiant\2025.1\synpbase #OS: Windows 10 or later #Hostname: D-GM0GK9EK # Mon Feb 9 10:40:04 2026 #Implementation: impl_1 Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys HDL Compiler, Version comp202409synp2, Build 155R, Built Jun 12 2025 08:34:14, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys VHDL Compiler, Version comp202409synp2, Build 155R, Built Jun 12 2025 08:34:14, @ @N|Running in 64-bit mode @N:Can't find top module! Top entity isn't set yet! @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.vhd'. VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) Process completed successfully. # Mon Feb 9 10:40:05 2026 ###########################################################] ###########################################################[ Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys Verilog Compiler, Version comp202409synp2, Build 155R, Built Jun 12 2025 08:34:14, @ @N|Running in 64-bit mode @I::"C:\lscc\radiant\2025.1\synpbase\lib\generic\lav-ate.v" (library work) @I::"C:\lscc\radiant\2025.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3275:17:3275:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3282:17:3282:28|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3339:17:3339:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3346:17:3346:28|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3401:17:3401:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3408:17:3408:28|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo_dc.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5142:25:5142:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5146:25:5146:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5177:29:5177:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5181:29:5181:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1060:25:1060:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1064:25:1064:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1095:29:1095:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1099:29:1099:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":730:25:730:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":734:25:734:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":767:29:767:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":771:29:771:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v":193:11:193:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v":202:11:202:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_true.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1880:29:1880:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1885:29:1885:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1920:33:1920:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1953:29:1953:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1958:29:1958:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1992:33:1992:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2502:29:2502:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2507:29:2507:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2538:33:2538:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2542:33:2542:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2575:29:2575:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2580:29:2580:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2611:33:2611:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2615:33:2615:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3097:29:3097:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3102:29:3102:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3133:33:3133:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3137:33:3137:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3170:29:3170:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3175:29:3175:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3206:33:3206:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3210:33:3210:44|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v":1485:25:1485:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v":1491:25:1491:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v":1402:25:1402:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v":1408:25:1408:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v":99:11:99:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v":970:25:970:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v":976:25:976:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work) @I::"D:\Avant_E70_Development_Board\test_project\Blinking Lights\Led.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 185MB) Process completed successfully. # Mon Feb 9 10:40:05 2026 ###########################################################] ###########################################################[ @I::"C:\lscc\radiant\2025.1\synpbase\lib\generic\lav-ate.v" (library work) @I::"C:\lscc\radiant\2025.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3275:17:3275:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3282:17:3282:28|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3339:17:3339:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3346:17:3346:28|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3401:17:3401:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo/rtl\lscc_fifo.v":3408:17:3408:28|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo_dc.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5142:25:5142:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5146:25:5146:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5177:29:5177:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/fifo_dc/rtl\lscc_fifo_dc.v":5181:29:5181:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1060:25:1060:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1064:25:1064:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1095:29:1095:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp/rtl\lscc_ram_dp.v":1099:29:1099:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":730:25:730:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":734:25:734:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":767:29:767:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dp/rtl\lscc_lfmxo4_ram_dp.v":771:29:771:40|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v":193:11:193:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_be.v":202:11:202:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_true.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1880:29:1880:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1885:29:1885:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1920:33:1920:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1953:29:1953:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1958:29:1958:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":1992:33:1992:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2502:29:2502:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2507:29:2507:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2538:33:2538:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2542:33:2542:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2575:29:2575:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2580:29:2580:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2611:33:2611:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":2615:33:2615:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3097:29:3097:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3102:29:3102:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3133:33:3133:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3137:33:3137:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3170:29:3170:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3175:29:3175:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3206:33:3206:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dp_true/rtl\lscc_ram_dp_true.v":3210:33:3210:44|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v":1485:25:1485:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/ram_dq/rtl\lscc_ram_dq.v":1491:25:1491:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v":1402:25:1402:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../LFMXO4/ram_dq/rtl\lscc_lfmxo4_ram_dq.v":1408:25:1408:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\pmi_ram_dq_be.v":99:11:99:22|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_rom.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v" (library work) @N: CG334 :"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v":970:25:970:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2025.1\ip\pmi\../common/rom/rtl\lscc_rom.v":976:25:976:36|Read directive translate_on. @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_lav-at.v":"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v" (library work) @I:"C:\lscc\radiant\2025.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2025.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work) @I::"D:\Avant_E70_Development_Board\test_project\Blinking Lights\Led.v" (library work) Verilog syntax check successful! Options changed - recompiling @N: CG364 :"D:\Avant_E70_Development_Board\test_project\Blinking Lights\Led.v":2:7:2:9|Synthesizing module led in library work. Running optimization stage 1 on led ....... Finished optimization stage 1 on led (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 187MB) Running optimization stage 2 on led ....... Finished optimization stage 2 on led (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 187MB) For a summary of runtime per design unit, please see file: ========================================================== @L: D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\synwork\layer0.duruntime At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 188MB) Process completed successfully. # Mon Feb 9 10:40:08 2026 ###########################################################] ###########################################################[ Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys Synopsys Netlist Linker, Version comp202409synp2, Build 155R, Built Jun 12 2025 08:34:14, @ @N|Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 153MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Feb 9 10:40:08 2026 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\synwork\LED_impl_1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 93MB peak: 93MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime Process completed successfully. # Mon Feb 9 10:40:09 2026 ###########################################################] ###########################################################[ Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys Synopsys Netlist Linker, Version comp202409synp2, Build 155R, Built Jun 12 2025 08:34:14, @ @N|Running in 64-bit mode File D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\synwork\LED_impl_1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 152MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Mon Feb 9 10:40:10 2026 ###########################################################] Premap Report # Mon Feb 9 10:40:11 2026 Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys Lattice Technology Pre-mapping, Version map202409latsp1, Build 075R, Built Jun 12 2025 06:33:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 202MB) Reading constraint file: C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl @L: D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\LED_impl_1_scck.rpt See clock summary report "D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\LED_impl_1_scck.rpt" @N: MF472 |Synthesis running in Automatic Compile Point mode @N: MF474 |No compile point is identified in Automatic Compile Point mode @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 202MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 202MB) Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 202MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 195MB peak: 202MB) NConnInternalConnection caching is on Starting HSTDM IP insertion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 246MB peak: 247MB) Finished HSTDM IP insertion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 246MB peak: 247MB) Started DisTri Cleanup (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 246MB peak: 247MB) Finished DisTri Cleanup (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 246MB peak: 247MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 248MB peak: 248MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 248MB peak: 248MB) @N: FX1184 |Applying syn_allowed_resources blockrams=990 on top level netlist led Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 248MB peak: 249MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------- 0 - led|osc_clk 200.0 MHz 5.000 inferred Inferred_clkgroup_0, Inferred_clkgroup_0_1 28 ======================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------- led|osc_clk 28 osc_clk(port) count_num[27:0].C - - ================================================================================================= @W: MT530 :"d:\avant_e70_development_board\test_project\blinking lights\led.v":19:0:19:5|Found inferred clock led|osc_clk which controls 28 sequential elements including count_num[27:0]. This clock has no specified timing constraint which may adversely impact design performance. ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 28 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @KP:ckid0_0 osc_clk port 28 count_num[27:0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 249MB peak: 249MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 249MB peak: 250MB) Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 250MB peak: 250MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 161MB peak: 251MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime # Mon Feb 9 10:40:16 2026 ###########################################################] Map & Optimize Report # Mon Feb 9 10:40:16 2026 Copyright (C) 1994-2025 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: W-2024.09LR-SP1-1 Install: C:\lscc\radiant\2025.1\synpbase OS: Windows 10 or later Hostname: D-GM0GK9EK Implementation : impl_1 Synopsys Lattice Technology Mapper, Version map202409latsp1, Build 075R, Built Jun 12 2025 06:33:45, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 202MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 189MB peak: 202MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 202MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 202MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 245MB peak: 245MB) Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 249MB peak: 249MB) Starting area decomp (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 249MB peak: 250MB) Finished area decomp (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 249MB peak: 250MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 249MB peak: 250MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 250MB peak: 250MB) Available hyper_sources - for debug and ip models None Found NConnInternalConnection caching is on @W: BN132 :"d:\avant_e70_development_board\test_project\blinking lights\led.v":19:0:19:5|Removing sequential instance count_num_0[27:0] because it is equivalent to instance count_num[27:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 352MB peak: 363MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 352MB peak: 363MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 352MB peak: 363MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 353MB peak: 363MB) Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 353MB peak: 363MB) Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 353MB peak: 363MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s 1.75ns 23 / 28 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 353MB peak: 363MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 354MB peak: 363MB) Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 354MB peak: 363MB) Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 354MB peak: 363MB) Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 312MB peak: 363MB) Writing Analyst data base D:\Avant_E70_Development_Board\test_project\Blinking Lights\LED\impl_1\synwork\LED_impl_1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 350MB peak: 363MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 351MB peak: 363MB) @N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 351MB peak: 363MB) Finished Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 351MB peak: 363MB) Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 350MB peak: 363MB) @W: MT420 |Found inferred clock led|osc_clk with period 5.00ns. Please declare a user-defined clock on port osc_clk. ##### START OF TIMING REPORT #####[ # Timing report written on Mon Feb 9 10:40:24 2026 # Top view: led Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\lscc\radiant\2025.1\scripts\tcl\flow\radiant_synplify_vars.tcl @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 1.319 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------- led|osc_clk 200.0 MHz 271.7 MHz 5.000 3.680 1.319 inferred Inferred_clkgroup_0, Inferred_clkgroup_0_1 System 200.0 MHz NA 5.000 NA NA system system_clkgroup ============================================================================================================================================ Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------- led|osc_clk led|osc_clk | 5.000 1.320 | No paths - | No paths - | No paths - ================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: led|osc_clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------ count_num[0] led|osc_clk FD1P3DX Q un5_count_num_1_axb_0 0.907 1.319 count_num[1] led|osc_clk FD1P3DX Q un5_count_num_1_axb_1 0.907 1.319 count_num[2] led|osc_clk FD1P3DX Q un5_count_num_1_axb_2 0.907 1.381 count_num[3] led|osc_clk FD1P3DX Q un5_count_num_1_axb_3 0.907 1.381 count_num[4] led|osc_clk FD1P3DX Q un5_count_num_1_axb_4 0.907 1.442 count_num[5] led|osc_clk FD1P3DX Q un5_count_num_1_axb_5 0.907 1.442 count_num[6] led|osc_clk FD1P3DX Q un5_count_num_1_axb_6 0.907 1.502 count_num[7] led|osc_clk FD1P3DX Q un5_count_num_1_axb_7 0.907 1.502 count_num[8] led|osc_clk FD1P3DX Q un5_count_num_1_axb_8 0.907 1.563 count_num[9] led|osc_clk FD1P3DX Q un5_count_num_1_axb_9 0.907 1.563 ================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------- count_num[26] led|osc_clk FD1P3DX D N_465[26] 4.946 1.319 count_num[24] led|osc_clk FD1P3DX D N_465[24] 4.946 1.381 count_num[25] led|osc_clk FD1P3DX D N_465[25] 4.946 1.381 count_num[22] led|osc_clk FD1P3DX D N_465[22] 4.946 1.442 count_num[20] led|osc_clk FD1P3DX D N_465[20] 4.946 1.502 count_num[21] led|osc_clk FD1P3DX D N_465[21] 4.946 1.502 count_num[16] led|osc_clk FD1P3DX D N_465[16] 4.946 1.625 count_num[17] led|osc_clk FD1P3DX D N_465[17] 4.946 1.625 count_num[14] led|osc_clk FD1P3DX D N_465[14] 4.946 1.685 count_num[12] led|osc_clk FD1P3DX D N_465[12] 4.946 1.746 ====================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.054 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.946 - Propagation time: 3.627 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.319 Number of logic level(s): 15 Starting point: count_num[0] / Q Ending point: count_num[26] / D The start point is clocked by led|osc_clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK The end point is clocked by led|osc_clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- count_num[0] FD1P3DX Q Out 0.907 0.907 r - un5_count_num_1_axb_0 Net - - - - 2 un5_count_num_1_cry_0_0 CCU2C A0 In 0.000 0.907 r - un5_count_num_1_cry_0_0 CCU2C COUT Out 0.900 1.807 r - un5_count_num_1_cry_1 Net - - - - 1 un5_count_num_1_cry_2_0 CCU2C CIN In 0.000 1.807 r - un5_count_num_1_cry_2_0 CCU2C COUT Out 0.061 1.868 r - un5_count_num_1_cry_3 Net - - - - 1 un5_count_num_1_cry_4_0 CCU2C CIN In 0.000 1.868 r - un5_count_num_1_cry_4_0 CCU2C COUT Out 0.061 1.929 r - un5_count_num_1_cry_5 Net - - - - 1 un5_count_num_1_cry_6_0 CCU2C CIN In 0.000 1.929 r - un5_count_num_1_cry_6_0 CCU2C COUT Out 0.061 1.990 r - un5_count_num_1_cry_7 Net - - - - 1 un5_count_num_1_cry_8_0 CCU2C CIN In 0.000 1.990 r - un5_count_num_1_cry_8_0 CCU2C COUT Out 0.061 2.051 r - un5_count_num_1_cry_9 Net - - - - 1 un5_count_num_1_cry_10_0 CCU2C CIN In 0.000 2.051 r - un5_count_num_1_cry_10_0 CCU2C COUT Out 0.061 2.112 r - un5_count_num_1_cry_11 Net - - - - 1 un5_count_num_1_cry_12_0 CCU2C CIN In 0.000 2.112 r - un5_count_num_1_cry_12_0 CCU2C COUT Out 0.061 2.173 r - un5_count_num_1_cry_13 Net - - - - 1 un5_count_num_1_cry_14_0 CCU2C CIN In 0.000 2.173 r - un5_count_num_1_cry_14_0 CCU2C COUT Out 0.061 2.234 r - un5_count_num_1_cry_15 Net - - - - 1 un5_count_num_1_cry_16_0 CCU2C CIN In 0.000 2.234 r - un5_count_num_1_cry_16_0 CCU2C COUT Out 0.061 2.295 r - un5_count_num_1_cry_17 Net - - - - 1 un5_count_num_1_cry_18_0 CCU2C CIN In 0.000 2.295 r - un5_count_num_1_cry_18_0 CCU2C COUT Out 0.061 2.356 r - un5_count_num_1_cry_19 Net - - - - 1 un5_count_num_1_cry_20_0 CCU2C CIN In 0.000 2.356 r - un5_count_num_1_cry_20_0 CCU2C COUT Out 0.061 2.417 r - un5_count_num_1_cry_21 Net - - - - 1 un5_count_num_1_cry_22_0 CCU2C CIN In 0.000 2.417 r - un5_count_num_1_cry_22_0 CCU2C COUT Out 0.061 2.478 r - un5_count_num_1_cry_23 Net - - - - 1 un5_count_num_1_cry_24_0 CCU2C CIN In 0.000 2.478 r - un5_count_num_1_cry_24_0 CCU2C COUT Out 0.061 2.539 r - un5_count_num_1_cry_25 Net - - - - 1 un5_count_num_1_cry_26_0 CCU2C CIN In 0.000 2.539 r - un5_count_num_1_cry_26_0 CCU2C S0 Out 0.481 3.021 r - un5_count_num_1_cry_26_0_S0 Net - - - - 1 count_num_3[26] LUT4 A In 0.000 3.021 r - count_num_3[26] LUT4 Z Out 0.606 3.627 r - N_465[26] Net - - - - 1 count_num[26] FD1P3DX D In 0.000 3.627 r - ============================================================================================= ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 351MB peak: 363MB) Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 351MB peak: 363MB) --------------------------------------- Resource Usage Report Part: lav_at_e70lfg1156c-3 Register bits: 28 of 397440 (0%) I/O cells: 18 Details: CCU2C: 14 FD1P3DX: 28 GSRA: 1 IB: 2 INV: 1 LUT4: 22 OB: 16 VHI: 1 VLO: 1 Resource Usage inside macros: Registers: 0 LUTs: 0 EBRs: 0 DSPs: 0 Distributed RAMs: 0 Carry Chains: 0 Blackboxes: 0 Mapping Summary: Total number of registers: 28 + 0 = 28 of 397440 (0.01%) Total number of LUTs: 22 + 0 = 22 Total number of EBRs: 0 + 0 = 0 of 990 (0.00%) Total number of DSPs: 0 + 0 = 0 of 1800 (0.00%) Total number of Distributed RAMs: 0 + 0 = 0 Total number of Carry Chains: 14 + 0 = 14 Total number of BlackBoxes: 3 + 0 = 3 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 229MB peak: 363MB) Process took 0h:00m:08s realtime, 0h:00m:08s cputime # Mon Feb 9 10:40:25 2026 ###########################################################]